We're working on the next generation of machine learning-based AI chipsets.

We're backed in funding from Elon Musk and Bill gates, working on never before seen technology.
Competitive salary, + equity.
Work with talented teams, along with a top-of-the-line leadership team.
Flexible schedule 1-3 days onsite each week.

ASIC designer strong with RTL, high-speed protocols such as Serdes, PCIe
Pluses: I3C, PCIe6, MIPI,
1-3 days onsite in either Mountain View California, or Austin Texas each week.

Full job description Below

Responsibilities:

• RTL designs for SoC interconnects, DMAs, and I/O Interface blocks.
• Front-end design flows using linting, placement-driven physical synthesis, timing closure, and power simulations.
• Implement UPF-based low power design methodology.
• Clock domain partitioning, implementations, and verifications of CDCs in the design.
• Define timing constraints for synthesis and P&R
• Design documentation and design reviews.
• Work closely with architecture, software, and modeling teams to ensure agile developments and design convergence.

Requirements
Required Qualifications and Skills:

• 5+ years of direct industry experience in digital and ASIC designs.
• 5+ design experience on ARM/AMBA/AXI, memory controller, Ethernet, PCIe, I2C, SPI.
• Good communication skills and willingness to work with others.

Additional Nice-to-Have Qualifications:

• Knowledge in ML algorithms
• Python, C/C++, SystemC