Physical Design Engineer

Semiconductor manufacturer seeks Physical Design Engineer

  • San Jose, CA
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A bit about us:

We are a global semiconductor and IP maker that advance data center connectivity and solve the bottleneck between memory and processing.

The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware.

Currently, we are on the hunt for a Physical Design Engineer with the following skill set...

Why join us?

  • Generous compensation package
  • Bonus
  • Equity
  • Matching 401(k)
  • Employee stock purchase plan
  • Comprehensive medical and dental benefits
  • PTO program and gym membership

Job Details

In this position, you will be working on the next generation multi-protocol SERDES Phy IP. The physical design engineer will have full ownership over the digital implementation of the IP subsystem design and / or integration. You will define the methodology for synthesis, power gated place and route, STA, EMIR, LEC, DRC and LVS, and also take full ownership of implementing IP RTL design to final GDSII. In addition, you will be expected to interact extensively with digital design analog and custom layout engineers in the team.

Here's what you'll need...
  • MSEE and 5+ years or BSEE and 8+ years
  • Strong understanding of the full design cycle from RTL to GDSII for digital-mixed signal IPs.
  • Experienced with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power/ power gating design techniques
  • High proficiency in PD EDA ecosystem, implementation flows and physical and timing signoff combined with excellent scripting skills (Perl, Tcl, Python). Cadence tool set experience is an advantage
  • Understanding of CAD automation methods.
  • Experienced with integration of analog blocks
  • Highly independent and capable of multi-tasking.

What you'll be doing...
  • Define IP floorplan
  • Collaborate with RTL designers to define timing constraints
  • Interact with custom layout and analog teams to align pinout and analog IP timing between netlist, LEF and .LIB
  • Develop, execute and optimize power gated place and route of digital blocks while meeting strict power-performance-area requirements
  • Static timing analysis and sign-off
  • Static and dynamic EM-IR analysis
  • Physical verification (DRC, ERC, LVS) at IP level

Easy Apply Now
Easy Apply Now
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