A bit about us:
A security processor company redefining hardware root of trust with hardware-based security technologies, including per-system AI.
Why join us?
Great product working on Security system processors and is an AI-powered engineer to prevent hackers. Great equity options based on experience, and working with a strong team in the bay area.
Job Details
ASIC/ SOC designer- RTL logic design and implementation, microarchitecture, timing closure, coding in verilog
Big plus for embedded CPU design.
Onsite in San Jose, California. Full Job description below.
Help develop the design and implementation of SoCs;
Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;
Work with FPGA engineers to perform early prototyping; and
Support test program development, chip validation, and chip life until production maturity.
Team Management and Building
Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
Qualifications
5+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
Proficient in writing clear, implementable micro-architecture specifications;
Expertise in writing efficient RTL code in Verilog;
Good understanding of assertions, coverage analysis, synthesis, and timing closure;
Experience in revision control, regression, and bug-tracking tools;
Fluency with scripting languages (e.g., Perl, Python);
Must have gone through at least one tape out;
Preferred: Lab debug/bring-up experience
ACADEMIC CREDENTIALS
BA or MS (preferred) degree in EE/EECS/CS or equivalent.
Big plus for embedded CPU design.
Onsite in San Jose, California. Full Job description below.
Help develop the design and implementation of SoCs;
Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;
Work with FPGA engineers to perform early prototyping; and
Support test program development, chip validation, and chip life until production maturity.
Team Management and Building
Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
Qualifications
5+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
Proficient in writing clear, implementable micro-architecture specifications;
Expertise in writing efficient RTL code in Verilog;
Good understanding of assertions, coverage analysis, synthesis, and timing closure;
Experience in revision control, regression, and bug-tracking tools;
Fluency with scripting languages (e.g., Perl, Python);
Must have gone through at least one tape out;
Preferred: Lab debug/bring-up experience
ACADEMIC CREDENTIALS
BA or MS (preferred) degree in EE/EECS/CS or equivalent.
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Sometimes Jobot is required to perform background checks with your authorization. Jobot will consider qualified candidates with criminal histories in a manner consistent with any applicable federal, state, or local law regarding criminal backgrounds, including but not limited to the Los Angeles Fair Chance Initiative for Hiring and the San Francisco Fair Chance Ordinance.
Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.
By applying for this job, you agree to receive calls, AI-generated calls, text messages, or emails from Jobot, and/or its agents and contracted partners. Frequency varies for text messages. Message and data rates may apply. Carriers are not liable for delayed or undelivered messages. You can reply STOP to cancel and HELP for help. You can access our privacy policy here: jobot.com/privacy-policy